? semiconductor components industries, llc, 2006 june, 2006 ? rev. 6 1 publication order number: MC14572UB/d MC14572UB hex gate the MC14572UB hex functional gate is constructed with mos p?channel and n?channel enhancement mode devices in a single monolithic structure. these complementary mos logic gates find primary use where low power dissipation and/or high noise immunity is desired. the chip contains four inverters, one nor gate and one nand gate. features ? diode protection on all inputs ? single supply operation ? supply voltage range = 3.0 vdc to 18 vdc ? nor input pin adjacent to v ss pin to simplify use as an inverter ? nand input pin adjacent to v dd pin to simplify use as an inverter ? nor output pin adjacent to inverter input pin for or application ? nand output pin adjacent to inverter input pin for and application ? capable of driving two low?power ttl loads or one low?power schottky ttl load over the rated temperature range ? pb?free packages are available* maximum ratings (voltages referenced to v ss ) parameter symbol value unit dc supply voltage range v dd ?0.5 to +18.0 v input or output voltage range (dc or transient) v in , v out ?0.5 to v dd + 0.5 v input or output current (dc or transient) per pin i in , i out 10 ma power dissipation, per package (note 1) p d 500 mw ambient temperature range t a ?55 to +125 c storage temperature range t stg ?65 to +150 c lead temperature (8?second soldering) t l 260 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliability. 1. temperature derating: plastic ?p and d/dw? packages: ? 7.0 mw/ c from 65 c to 125 c this device contains protection circuitry to guard against damage due to high static voltages or electric fields. however, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high?impedance circuit. for proper operation, v in and v out should be constrained to the range v ss (v in or v out ) v dd . unused inputs must always be tied to an appropriate logic voltage level (e.g., either v ss or v dd ). unused outputs must be left open. *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. device package shipping ? ordering information MC14572UBcp pdip?16 25 units / rail MC14572UBd soic?16 48 units / rail MC14572UBdr2 soic?16 2500/tape & ree l MC14572UBf soeiaj?16 http://onsemi.com ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our t ape and reel packaging specification s brochure, brd8011/d. 50 units / rail MC14572UBdr2g soic?16 (pb?free) 2500/tape & ree l MC14572UBdg soic?16 (pb?free) 48 units / rail MC14572UBcpg pdip?16 (pb?free) 25 units / rail a = assembly location wl, l = wafer lot yy, y = year ww, w = work week g = pb?free package marking diagrams pdip?16 p suffix case 648 soic?16 d suffix case 751b 1 16 14572ubg awlyww soeiaj?16 f suffix case 966 1 16 MC14572UB alywg 16 1 MC14572UBcp awlyywwg 1 1 1
MC14572UB http://onsemi.com 2 pin assignment 13 14 15 16 9 10 11 12 5 4 3 2 1 8 7 6 in e out f in 1 f in 2 f v dd out d in d out e in b out b in a out a v ss in 2 c in 1 c out c logic diagram 15 14 12 10 7 6 4 2 13 11 9 5 3 1 v dd = pin 16 v ss = pin 8 circuit schematic v dd v dd v dd 2 7 6 1 5 14 15 13 v ss v ss v ss
MC14572UB http://onsemi.com 3 ????????????????????????????????? ????????????????????????????????? (voltages referenced to v ss ) characteristic symbo l v dd vdc ? 55 c 25 c 125 c unit min max min typ (note 2) max min max output voltage ?0? level v in = v dd or 0 v ol 5.0 10 15 ? ? ? 0.05 0.05 0.05 ? ? ? 0 0 0 0.05 0.05 0.05 ? ? ? 0.05 0.05 0.05 vdc v in = 0 or v dd ?1? level v oh 5.0 10 15 4.95 9.95 14.95 ? ? ? 4.95 9.95 14.95 5.0 10 15 ? ? ? 4.95 9.95 14.95 ? ? ? vdc input voltage ?0? level (v o = 4.5 or 0.5 vdc) (v o = 9.0 or 1.0 vdc) (v o = 13.5 or 1.5 vdc) v il 5.0 10 15 ? ? ? 1.0 2.0 2.5 ? ? ? 2.25 4.50 6.75 1.0 2.0 2.5 ? ? ? 1.0 2.0 2.5 vdc ?1? level (v o = 0.5 or 4.5 vdc) (v o = 1.0 or 9.0 vdc) (v o = 1.5 or 13.5 vdc) v ih 5.0 10 15 4.0 8.0 12.5 ? ? ? 4.0 8.0 12.5 2.75 5.50 8.25 ? ? ? 4.0 8.0 12.5 ? ? ? vdc output drive current (v oh = 2.5 vdc) source (v oh = 4.6 vdc) (v oh = 9.5 vdc) (v oh = 13.5 vdc) i oh 5.0 5.0 10 15 ? 1.2 ? 0.25 ? 0.62 ? 1.8 ? ? ? ? ? 1.0 ? 0.2 ? 0.5 ? 1.5 ? 1.7 ? 0.36 ? 0.9 ? 3.5 ? ? ? ? ? 0.7 ? 0.14 ? 0.35 ? 1.1 ? ? ? ? madc (v ol = 0.4 vdc) sink (v ol = 0.5 vdc) (v ol = 1.5 vdc) i ol 5.0 10 15 0.64 1.6 4.2 ? ? ? 0.51 1.3 3.4 0.88 2.25 8.8 ? ? ? 0.36 0.9 2.4 ? ? ? madc input current i in 15 ? 0.1 ? 0.00001 0.1 ? 1.0 adc input capacitance (v in = 0) c in ? ? ? ? 5.0 7.5 ? ? pf quiescent current (per package) i dd 5.0 10 15 ? ? ? 0.25 0.5 1.0 ? ? ? 0.0005 0.0010 0.0015 0.25 0.5 1.0 ? ? ? 7.5 15 30 adc total supply current (notes 3, 4) (dynamic plus quiescent, per package) (c l = 50 pf on all outputs, all buffers switching) i t 5.0 10 15 i t = (1.89 a/khz) f + i dd i t = (3.80 a/khz) f + i dd i t = (5.68 a/khz) f + i dd adc 2. data labelled ?typ? is not to be used for design purposes but is intended as an indication of the ic?s potential performance. 3. the formulas given are for the typical characteristics only at 25 c. 4. to calculate total supply current at loads other than 50 pf: i t (c l ) = i t (50 pf) + (c l ? 50) vfk where: i t is in a (per package), c l in pf, v = (v dd ? v ss ) in volts, f in khz is input frequency, and k = 0.006.
MC14572UB http://onsemi.com 4 ????????????????????????????????? ????????????????????????????????? (type 5) (c l = 50 pf, t a = 25 c) characteristic symbol v dd min typ (note 6) max unit output rise time t tlh = (3.0 ns/pf) c l + 30 ns t tlh = (1.5 ns/pf) c l + 15 ns t tlh = (1.1 ns/pf) c l + 10 ns t tlh 5.0 10 15 ? ? ? 180 90 65 360 180 130 ns output fall time t thl = (1.5 ns/pf) c l + 25 ns t thl = (0.75 ns/pf) c l + 12.5 ns t thl = (0.55 ns/pf) c l + 9.5 ns t thl 5.0 10 15 ? ? ? 100 50 40 200 100 80 ns propagation delay time t plh , t phl = (1.7 ns/pf) c l + 5 ns t plh , t phl = (0.66 ns/pf) c l + 17 ns t plh , t phl = (0.5 ns/pf) c l + 15 ns t plh , t phl 5.0 10 15 ? ? ? 90 50 40 180 100 80 ns 5. the formulas given are for the typical characteristics only at 25 c. 6. data labelled ?typ? is not to be used for design purposes but is intended as an indication of the ic?s potential performance. figure 1. switching time test circuits and waveforms pulse generator pulse generator input 2 input 15 v dd v dd 16 16 8 8v ss v ss c l c l 1 13 output output pulse generator input 7 v dd 16 5 output 8v ss c l 6 20 ns 20 ns v dd v ss v oh v ol t r t f 90% 50% 10% 90% 50% 10% 90% 50% 10% 90% 10% 50% input output t phl t plh 14
MC14572UB http://onsemi.com 5 package dimensions notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. ?a? b f c s h g d j l m 16 pl seating 18 9 16 k plane ?t? m a m 0.25 (0.010) t dim min max min max millimeters inches a 0.740 0.770 18.80 19.55 b 0.250 0.270 6.35 6.85 c 0.145 0.175 3.69 4.44 d 0.015 0.021 0.39 0.53 f 0.040 0.70 1.02 1.77 g 0.100 bsc 2.54 bsc h 0.050 bsc 1.27 bsc j 0.008 0.015 0.21 0.38 k 0.110 0.130 2.80 3.30 l 0.295 0.305 7.50 7.74 m 0 10 0 10 s 0.020 0.040 0.51 1.01 pdip?16 case 648?08 issue t soic?16 case 751b?05 issue j notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 18 16 9 seating plane f j m r x 45 g 8 pl p ?b? ?a? m 0.25 (0.010) b s ?t? d k c 16 pl s b m 0.25 (0.010) a s t dim min max min max inches millimeters a 9.80 10.00 0.386 0.393 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.229 0.244 r 0.25 0.50 0.010 0.019
MC14572UB http://onsemi.com 6 package dimensions soeiaj?16 case 966?01 issue a h e a 1 dim min max min max inches ??? 2.05 ??? 0.081 millimeters 0.05 0.20 0.002 0.008 0.35 0.50 0.014 0.020 0.10 0.20 0.007 0.011 9.90 10.50 0.390 0.413 5.10 5.45 0.201 0.215 1.27 bsc 0.050 bsc 7.40 8.20 0.291 0.323 0.50 0.85 0.020 0.033 1.10 1.50 0.043 0.059 0 0.70 0.90 0.028 0.035 ??? 0.78 ??? 0.031 a 1 h e q 1 l e 10 0 10 l e q 1 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions d and e do not include mold flash or protrusions and are measured at the parting line. mold flash or protrusions shall not exceed 0.15 (0.006) per side. 4. terminal numbers are shown for reference only. 5. the lead width dimension (b) does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the lead width dimension at maximum material condition. dambar cannot be located on the lower radius or the foot. minimum space between protrusions and adjacent lead to be 0.46 ( 0.018). m l detail p view p c a b e m 0.13 (0.005) 0.10 (0.004) 1 16 9 8 d z e a b c d e e l m z on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, r epresentation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actu al performance may vary time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical impla nt into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a situation wh ere personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its offic ers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any clai m of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5773?3850 MC14572UB/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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